WAMCA 2019

10th Workshop on Applications for Multi-Core Architectures
October 15-18, 2019
Federal University of Mato Grosso do Sul, Campo Grande, BRAZIL

Held in conjunction with the
31th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2019)

Since the advent of the multi-core concept, significant advances have been made on many of the related aspects. Multi-core has become a natural element in the HPC ecosystem, and its pervasiveness within the landscape of common computing devices has made it a standard. Therefore, hardware and software concerns related to multi-core are good targets for computer science investigations, with a high potential for a genuine contribution. Beside the plethora of applications for which more powerful solutions are still expected, efficient implementation techniques for many-core chip processors are of keen interest. WAMCA is aiming at providing an opportunity to address all aforementioned technical challenges and more, including reports on specific case studies. This workshop is an opportunity for application designers and computer architects to discuss new techniques and emerging applications as well as their implications on current and next-generation many-core architectures. Authors are invited to submit manuscripts reporting a technical contribution on multi-core related topics. Aspects of interest include (but are not limited to):
  • Multithread parallelisation
  • Scalability issues
  • Case study
  • Hybrid parallelisation
  • NUMA manycore implementation
  • Benchmarking and runtime analysis
  • Frameworks and tools
  • Foundation of shared memory computing
Important Dates
  • Paper deadline : September 06, 2019 (For newer submissions!)
  • Author notification : August 27, 2019
  • Camera ready : September 06, 2019
  • PS: Due to the extension of the camera ready deadline, we are accepting new submissions until september 06, the corresponding papers will be directely considered for evaluation.

Submissions must be in English, 8 pages maximum, following the IEEE conference formatting guidelines (submission). All accepted papers will be published at IEEE Xplore and selected ones will be considered for a publication in top ranked HPC journal.

General Chair
Claude Tadonki (MINES ParisTech - PSL)  (claude.tadonki@mines-paristech.fr)
Workshop Chairs
Cristiana Bentes (State University of Rio de Janeiro)
Gabriele Mencagli (University of Pisa - Italy)
Lucia Drummond (Fluminense Federal University)
Mauricio Pilla (Federal University of Pelotas)
Program Chairs
Maria Clicia Castro (State University of Rio de Janeiro)
Guido Araujo (State University of Campinas)
Phillippe Navaux (Federal University of Rio Grande do Sul)
Ricardo Farias (Federal University of Rio de Janeiro)

Program Committee
Alexandre Gonçalves (IFRJ - Brazil)
Andre Rauber Du Bois (UFPEL - Brazil)
Corinne Ancourt (Mines ParisTech - France)
Denis Barthou (INRIA - France)
Diego Brandao (CEFET-RJ - Brazil)
Diego Dutra (UFRJ - Brazil)
Eyder Rios (UESPI - Brazil)
Guido Araujo (UNICAMP - Brazil)
Guilherme Cox (Rutgers University - US)
Henrique Freitas (PUC MG - Brazil)
Igor Machado (UERJ - Brazil)
Juliana Silva Zamith (UFRRJ - Brazil)
Khaled Ibrahim (Lawrence Berkeley National Lab - USA)
Konstantin Petrov (INRIA - France)
Leandro Marzulo (UERJ - Brazil)
Leonel Sousa (INESC-ID - Portugal)
Mauricio Pilla (UFPEL - Brazil)
Marcelo Zamith (UFRRJ - Brazil)
Marcin Paprzycki (IBS PAN and WSM - Poland)
Mitsuhisa Sato (RIKEN AICS / University of Tsukuba - Japan)
Rodolfo Azevedo (UNICAMP - Brazil)
Sandro Rigo (UNICAMP - Brazil)

Cutting-edge Techniques for Performance and Scalability on Manycore Machines
High Performance Computing (HPC) aims at providing reasonably fast computing solutions to scientific and real life problems. Many efforts have been made on the way to powerful supercomputers, including generic and customized configurations. The advent of multicore architectures is noticeable in the HPC history, because it has brought the underlying parallel programming concept into common considerations. Based on multicore processors, probably enhanced with acceleration units, current generation of supercomputers is rated to deliver an increasing peak performance, the Exascale era being the current horizon. However, getting a high fraction of the available peak performance is more and more difficult. The Design of an efficient code that scales well on a supercomputer is a non-trivial task. Manycore processors are now common, and the scalability issue in this context is crucial. Code optimization requires advanced programming techniques, taking into account the specificities and constraints of the target architecture. Many challenges are to be considered from the standpoint of efficiency and expected performances. This talk will provide a synopsis of the key aspects related to parallel processing efficiency (parallel programming paradigms, code transformations, code optimization), driven by selected case studies (image processing, particles physics, combinatorial algorithms).
Claude Tadonki, MINES ParisTech Institute (Paris/France)
Claude Tadonki is currently senior researcher and lecturer at MINES ParisTech Institute (Paris/France). He got its PhD and its Habilitation in computer science from the University of Rennes and the University of Paris-Sud respectively. After six years of cutting-edge research in operational research and theoretical computer science at the University of Geneva (Switzerland), he relocated to France to work for EMBL, University of Paris-Sud, LAL-CNRS and then MINES ParisTech. His main research topics included High Performance Computing, Combinatorial algorithms, and Operational Research. Claude Tadonki has worked at/with several laboratories and universities, has initiated various scientific projects and national/international collaborations, has given significant number of CS courses in different contexts including industries. He acts as a reviewer for high-impact international journals and major conferences, and he has published numerous papers in journals and conferences. He has actively participated and co-organized number of international HPC conferences.